In general, semiconductor devices or integrated circuits (ICs) can utilize selective oxidation, such as, local oxidation of silicon (LOCOS) to create isolation structures. LOCOS is often employed to electrically insulate or isolate various portions or structures of the semiconductor device from other portions of the device. LOCOS typically involves growing a pad oxide or liner oxide, depositing a hard mask layer over the liner oxide, etching the hard mask layer, and growing an oxide isolation structure. The hard mask layer can be a nitride film. The oxide structure can be grown by heating the substrate.
Isolation regions or structures for semiconductor devices can vary in size depending on parameters or requirements necessary for proper electric isolation and charge carrier isolation. For example, in memory devices, such as, flash electrical erasable programmable read only memories (flash EEPROMS), larger isolation structures are needed in peripheral areas (non-core areas for input/output circuitry) of the devices where larger voltages are present. In contrast, smaller isolation structures are utilized in core areas (e.g., the memory cell array) where memory cells are packed closely together and operate at lower voltage levels. Thus, certain areas of the semiconductor device can require large isolation structures while other areas can require small isolation structures due to different voltage requirements, dopant types, increased circuit packing density, dopant concentrations, or other criteria associated with IC design.
Heretofore, semiconductor devices, such as, flash memories generally have utilized thick LOCOS structures in peripheral regions and thin LOCOS structures in core regions. The thin and thick LOCOS structures require two separate critical masks to define the oxide structures which are grown in two separate selective oxidation processes. With reference to FIGS. 1-6, a conventional process for forming thin and thick oxide structures is described as follows.
In FIG. 1, a semiconductor structure device 12 includes a core region 8 and a peripheral region 9 separated by an interface 10. Structure 12 includes a substrate or base 14, a pad oxide layer 16, and a nitride layer 18. Structure 12 is first etched in accordance with a preliminary mask or zero layer mask (not shown) for defining alignment marks.
In FIG. 2, a source drain mask layer 20 is provided over layer 18 to define source and drain regions in peripheral region 9. Layer 20 completely covers core region 8. After layer 20 is applied, structure 12 is etched to remove layer 18 from portions of region 9 in accordance with layer 20. In FIG. 3, layer 20 is stripped from structure 12, and structure 12 is oxidized to form LOCOS isolation structure 24 in accordance with a conventional LOCOS technique. During this step, layer 18 in core region 8 is also oxidized. Additionally, LOCOS structure 24 is relatively thin at boundary or interface 10 with respect to the remaining portion of peripheral region 9.
In FIG. 4, a source drain mask layer 26 is applied to define source and drain regions in core region 8 as well as isolation structures for core region 8. In FIG. 5, structure 12 is etched in accordance with layer 26 to remove portions of layer 18 in core region 8. However, due to alignment errors, portions of structure 24 close to interface 10 can be etched because layer 26 does not reach interface 10 (FIG. 4). The etching of structure 12 can thin the thickness of structure 24 in peripheral region 9. This thinning can cause a step 28 and a groove 30. The thickness of structure 24 can be less than 1300 .ANG. at step 28. In FIG. 6, isolation structures 40 and 42 are grown in a thermal process in accordance with a conventional LOCOS technique. Step 28 and groove 30 remain on structure 10. The thickness of structure 28 can be less than 1000 .ANG. at groove 28.
Step 28 and groove 30 can cause residue or "stringer" problems during subsequent first polysilicon, oxygen-nitride-oxygen (ONO), second polysilicon and self-aligned etched (SAE) processes. Conductive material trapped in step 28, groove 30 can create unintentional gate structures due to the thinness of structure 24 or can electrically short adjacent structures.
Additionally, during the process discussed with reference to FIGS. 1-6, layer 18 is subjected to two oxidation steps which can create "oxide bumps" on top of "birds beaks" associated with structures 40 and 42. The oxide bumps can be due to material surface stress of layer 18 which is caused by the dual oxidation process associated with the formation of structures 24, 40 and 42. Step 28 can also create a "race track" topography problem related to the difference in thickness of structure 24 at interface 10. The race track topography problem is manifested when photoresist is provided on structure 12 and includes grooves or lanes in a race track form.
Thus, there is a need for a semiconductor device including thick and thin isolation structures with minimal step changes in an interface region between a peripheral region and a core region. Further, there is a need for a method of manufacturing an integrated circuit with thick and thin isolation structures which does not stress a hard mask layer in the core region. Further still, there is a need for a method of fabricating thick and thin LOCOS structures which is less susceptible to "race track" problems, "stringer" problems, and "oxide bump" problems.